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| HANBit HSD32M64D8KP Synchronous DRAM Module 256Mbyte (32Mx64bit),DIMM Unbuffered with Based on Stacked 16Mx8, 4Banks, 4K Ref., 3.3V Part No. HSD32M64D8KP GENERAL DESCRIPTION The HSD32M64D8KP is a 32M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of sixteen CMOS 16M x 8 bit(stacking chip) with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD32M64D8KP is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible. FEATURES * Part Identification HSD32M64D8KP - 10L HSD32M64D8KP - 13 * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * The used device is 4M x 8bit x 4Banks SDRAM : 100MHz ( CL=3) : 133MHz ( CL=3) URL:www.hbe.co.kr -1- HANBiT Electronics Co., Ltd HANBit PIN ASSIGNMENT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 Vss NC NC Vcc /WE DQM0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol DQM1 /CS0 NC Vss A0 A2 A4 A6 A8 A10 BA1 Vcc Vcc CLK0 Vss NC /CS2 DQM2 DQM3 NC Vcc NC NC CB2 CB3 Vss DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol DQ18 DQ19 Vcc DQ20 NC NC /CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss CLK2 NC WP SDA SCL Vcc PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Symbol Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 Vss NC NC Vcc /CAS DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 HSD32M64D8KP Symbol DQM5 /CS1 /RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vcc CLK1 NC Vss CKE0 /CS3 DQM6 DQM7 NC Vcc NC NC CB6 CB7 Vss DQ48 DQ49 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol DQ50 DQ51 Vcc DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss CLK3 NC SA0 SA1 SA2 Vcc URL:www.hbe.co.kr -2- HANBiT Electronics Co., Ltd HANBit FUNCTIONAL BLOCK DIAGRAM HSD32M64D8KP Vcc Vcc URL:www.hbe.co.kr -3- HANBiT Electronics Co., Ltd HANBit PIN FUNCTION DESCRIPTION PIN CLK /CE CKE NAME System clock Chip enable Clock enable HSD32M64D8KP INPUTT FUNCTION Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) A0 ~ A11 BA0 ~ BA1 /RAS /CAS Address Bank select address Row address strobe Column strobe Address /WE DQM0 ~ 7 Write enable Data mask input/output DQ0 ~ 63 Vcc/Vss Data input/output Power supply/ground Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1.0V to 4.6V -1.0V to 4.6V 16W -55oC to 150oC Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C)) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input leakage current URL:www.hbe.co.kr SYMBOL Vcc VIH VIL VOH VOL I LI MIN 3.0 2.0 -0.3 2.4 -10 TYP. 3.3 3.0 0 - MAX 3.6 Vcc+0.3 0.8 0.4 10 UNIT V V V V V uA NOTE 1 2 IOH = -2mA IOL = 2mA 3 -4- HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE, CKE CKE /CS DQM Address DQ (DQ0 ~ DQ7) SYMBOL CCLK CIN CCKE CCS CDQM CADD COUT MIN 10 40 10 10 5 40 64 MAX 14 60.8 15.2 15.2 7.6 60.8 96 UNITS pF pF pF pF pF pF pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70C) TEST PARAMETER Operating current (One bank active) Precharge standby current in power-down mode SYMBOL CONDITION Burst length = 1 tRC tRC(min) IO = 0mA CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) CS* VIH(min), tCC=10ns Input signals are changed one time during 20ns CKE VIH(min) CLK VIL(max), tCC= Input signals are stable CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), CS*VIH(min), tCC=10ns Input signals are changed one time during 20ns CKEVIH(min) CLK VIL(max), tCC= Input signals are stable IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C -13 1440 32 32 -10L 1440 mA mA mA VERSION UNIT E 1 NOT ICC1 ICC2P ICC2PS Precharge standby current in non power-down mode ICC2N 320 mA 160 80 mA 80 ICC2NS Active standby current in power-down mode ICC3P ICC3PS Active standby current in non power-down mode (One bank active) ICC3N 480 mA 400 ICC3NS Operating current (Burst mode) Refresh current Self refresh current ICC4 ICC5 ICC6 1760 3200 32 1600 3040 mA mA mA 1 2 URL:www.hbe.co.kr -5- HANBiT Electronics Co., Ltd HANBit L Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). HSD32M64D8KP 12.8 AC OPERATING TEST CONDITIONS (vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V +3.3V 1200 DOUT 870 50pF* VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA DOUT Z0=50 Vtt=1.4V 50 50pF (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data SYMBOL tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max) tRC(min) VERSION -13 15 20 20 45 100 65 2 2 CLK + 20 ns 1 1 1 2 70 -10L 20 20 20 50 UNIT ns ns ns ns ns ns CLK CLK CLK CLK ea NOTE 1 1 1 1 1 2 tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 2 2 3 4 URL:www.hbe.co.kr -6- HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -75 PARAMETER CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=3 CAS latency=3 SYMBOL MIN tCC tSAC tOH tCH tCL tSS tSH tSLZ tSHZ 3 2.5 2.5 1.5 0.8 1 5.4 7.5 MAX 1000 5.4 3 3 3 2 1 1 6 MIN 10 MAX 1000 6 ns ns ns ns ns ns ns ns ns 1 1,2 2 3 3 3 3 3 2 -10L UNIT NOTE CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output CAS latency=3 in Hi-Z Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE COMMAND Register Mode register set Auto refresh Entry Refresh Self refres h Exit CKE n-1 H H CKE n X H L H H Bank active & row address. Auto precharge disable Auto precharge disable Auto precharge disable H X L X L X H X H X V Row address /C S L L L L /R A S L L H /C A S L L H /W E L H H X X 3 D Q M X X BA 0,1 A10/ AP OP code X A11 A9~A0 NOTE 1,2 3 3 3 Read & column address Write & column L H X L H L H X V H H X L H L L X V L Column Address (A0 ~ A9) Column Address 4 4,5 4 URL:www.hbe.co.kr -7- HANBiT Electronics Co., Ltd HANBit address Burst Stop Precharg e Bank selection All banks Entry Exit Precharge power down mode Entry Exit DQM No operation command Auto precharge enable H H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X HSD32M64D8KP H X V X L H X X (A0 ~ A9) 4,5 6 Clock suspend or active power down X X V X X X 7 (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) URL:www.hbe.co.kr -8- HANBiT Electronics Co., Ltd HANBit TIMING DIAGRAM HSD32M64D8KP URL:www.hbe.co.kr -9- HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 10 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 11 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 12 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 13 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 14 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 15 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 16 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 17 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 18 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 19 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 20 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 21 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 22 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 23 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 24 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 25 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 26 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP * All banks precharge should be completed before Mode Resister Set cycle and auto refresh cycle --MODE RESISTER SET CYCLE-*Note : 1. /CS, /RAS, /CAS, /WE activation at the same clock cycle with address key will set internal mode resister 2.Minimum 2 clock cycle should be met before new /RAS activation. 3.Please refer to Mode Resister Set table URL:www.hbe.co.kr - 27 - HANBiT Electronics Co., Ltd HANBit PACKAGING INFORMATION Unit : mm HSD32M64D8KP Front View Rear View ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE MAX.frq CL3 133MHz CL3 100MHz HSD32M64D8KP-13 HSD32M64D8KP-10L 256MByte 256MByte 32M x64 32M x 64 168 Pin-DIMM 168 Pin-DIMM 4K 4K 3.3V 3.3V SDRAM SDRAM URL:www.hbe.co.kr - 28 - HANBiT Electronics Co., Ltd HANBit HSD32M64D8KP URL:www.hbe.co.kr - 29 - HANBiT Electronics Co., Ltd |
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